FIG. 1 illustrates a schematic block diagram of a computing system 10 and a corresponding boot up process for the computing system and video graphics cards wherein the boot up is in accordance with the PCI local bus spec 2.1 and VGA video bus specification (i.e., Interrupt 10H). As shown, the computing system 10 includes a central processing unit 12, a system BIOS module 14, system memory 16, a first video graphics card 18 and may also include a second video graphics card 20. Note, however, that many computing systems only include one video graphics card.
The video graphics card 18 includes a ROM 22 and a graphics controller circuit 24. The ROM 22 stores a video graphics boot up algorithm and is identified with a header that includes a flag "55AA" followed by the length of the ROM. Note that the ROM 22 may alternatively be part of the system BIOS module 14. The graphics controller 24 includes a frame buffer 26 for storing RGB data that is to be provided to a monitor. The graphics controller 24 further includes configuration space 28, which is arranged in accordance with the PCI spec 2.1. As such, the configuration space 28 includes a vender ID field, a device ID field, a command field, status field, vision ID field, class code field and header type fields. In addition, the configuration space 28 includes an assigned address field 30, which stores the address of system memory 16 in which the boot up algorithm is stored.
At the initial boot up of the computing system 10, the system BIOS module 14 executes the boot up algorithm stored in the reserved boot up memory 32 of system memory 16. The reserved boot up memory 32 includes one megabyte of space for storing a plurality of boot up algorithms, where physical or virtual memory locations C000-CFFF are reserved for the video graphics boot up algorithm. Such memory allocation is based on the interrupt 10-H video specification.
During the boot up process, the system BIOS module 14 causes the boot up algorithm stored in ROM 22 to be written into system memory at the assigned address stored in the configuration space at field 30. Having copied the boot up algorithm of the video graphics card into the system memory 16 at the assigned address, the algorithm is again copied, or remapped, into system memory at C00-CFFF to conform with the 10-H interrupt requirements. Thus, the video graphics boot up algorithm is actually, or effectively, copied twice, first into the allocated memory 34, and second into the reserved boot up memory 32.
After the video graphic boot up algorithm is executed, the system finishes the initial boot up process in a DOS mode. As such, text is displayed. Once the initial boot up process has ended, the operating system boot up process commences. During the operating system boot up process, the video graphics circuit is initiated to perform graphics operations, but limited to DOS parameters. In addition, because the video graphics boot up is limited to 32 to 64 kilobits of memory and requires VGA controller functionality, it has limited functional capabilities, which limits the speed and graphics options at which a computer can boot up.
Therefore, a need exists for a method and apparatus that allows the video graphics card to boot up in a graphics mode thus providing a boot up process for a computing system that includes enhanced graphics and increased speed.